Applications Engineer - Silicon IP
Position Summary & Responsibilities
Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.
About the Role
We’re looking for an Applications Engineer who will help customers successfully evaluate, integrate, verify, and physically implement our silicon IP in their SoCs. You’ll be the technical bridge between customers and our design, verification, physical design, and characterization teams—helping customers stand up verification environments, close coverage and timing, resolve integration issues, and keep tapeouts on schedule. This customer-facing role combines broad ASIC/SoC expertise, hands-on problem solving, and clear technical communication.
What You’ll Do
- Serve as the primary technical point of contact for customers integrating our silicon IP, from RTL simulation and UVM testbench setup through synthesis, floorplanning, place-and-route, timing closure, and signoff.
- Debug customer-reported issues across the RTL, testbench, constraints, and physical implementation boundary; distinguish IP defects and deliverable issues from configuration errors, protocol misunderstandings, constraints, or implementation choices.
- Develop and maintain reference verification environments, example testbenches, implementation flows, floorplan guidance, and integration collateral—including SDC and UPF templates—that reduce customer ramp time.
- Deliver onsite and remote technical training on IP architecture, verification methodology, verification IP usage, coverage closure, timing models, physical abstracts, and implementation best practices.
- Partner with engineering and product leaders to aggregate field evidence, prioritize corrective work, and shape future
Key Role Competencies & Evaluation Highlights
Evaluating architectural innovation in hardware-software co-design to achieve ultra-low power compute efficiency.
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