Lead Digital Verification Engineer

🏢 Efficientcomputer · 📍 San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX 💰 $200,000 - $260,000 / yr

⚡ Direct Talent Broker Referral

Why apply through CandidatesReach?

✔ Tailored Executive Endorsement Letter: Highlight your real strengths and verified background directly to hiring leads.

✔ Your Preferred Screening Terms: Choose between a 1-minute quick phone screen or scheduled email calendar.

✔ $500 Cash Hiring Bonus: Receive $500 direct cash reward after 30 days of active employment.

Position Summary & Responsibilities

Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.

We are looking for an experienced Design Verification Lead to drive the functional verification of complex SoC/IP designs from specification through tapeout in a newly formed hardware engineering organization. You will own the verification strategy, define methodology standards, build and guide a team of verification engineers, and serve as the final authority on verification quality and sign-off readiness. This role demands a strong blend of technical depth in modern verification methodologies (UVM, embedded C and compiler generated trace driven testing) and the leadership ability to execute across a multi-block chip program on schedule The DV Lead will help shape our internal processes for building robust and verified designs, including the company’s second product line, which will scale computing performance and capability, while improving energy efficiency.

This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones
Author and review verification plans mapping specifications to features, stimulus strategies(traditional stimulus generation, compiler driven), coverage goals, and sign-off criteria
Architect scalable UVM-based testbench environments including agents,

🎯 Candidate Preparation Guide For Efficientcomputer Applicants

Key Role Competencies & Evaluation Highlights

Key Role Focus:

Evaluating architectural innovation in hardware-software co-design to achieve ultra-low power compute efficiency.

📋 Preparation Priorities (Key Areas to Clarify):

1. Relying solely on brute-force scaling or standard CPU/GPU optimization techniques
2. Failing to understand the practical software stack implications of novel hardware
3. Treating power optimization as an afterthought rather than a core design constraint

✨ Recommended Role Alignment Hook:

I design compute systems from the transistor up to the compiler to fundamentally break the power wall in modern hardware.

🔒 Free Candidate Preparation Access

Unlock Preparation Priorities & Alignment Hook

🤝 Talent Broker Referral · $500 Bonus Included

Apply for Lead Digital Verification Engineer

Setup your contact terms & referral note to get recommended directly to the hiring lead at Efficientcomputer.

⚡ Continue with Google (Instant Setup)

or with email

Already have an account? Sign in here